1. Field of the Invention
The present invention relates to the erase mode in a flash memory array. More particularly, the present invention relates to a page erase mode and multiple page erase mode in a flash memory array.
2. The Prior Art
In a conventional flash memory array, the flash memory array is typically arranged as a matrix of wordlines and bitlines to form intersections with flash memory elements disposed at the intersections in a manner well known to those of ordinary skill in the art. The operations that may be performed on the memory cells in the flash memory array are READ, PROGRAM and ERASE.
The PROGRAM operation is often performed by driving selected bitlines connected to the drain region in the flash memory cells to a first voltage and driving the control gates of the flash memory cells connected to selected wordlines to a higher voltage to perform hot electron injection in a manner well known to those of ordinary skill in the art.
The ERASE operation is performed by driving the control gate of the flash memory cell to a voltage that is substantially less than a voltage placed on the bitline. In doing so, electrons are tunneled off of the floating gate of the flash memory cells in a manner well known to those of ordinary skill in the art. For conventional flash memory arrays, it is known that either the entire flash memory array may be erased at one time, known as BULK ERASE, or that a sector in the flash memory array may be erased at one time, known as SECTOR ERASE. An example of a BULK ERASE of a flash memory array is found in the paper "A 90 ns 100 K Erase-Program Cycle Megabit Flash Memory", 1989, IEEE International Solid State Circuits Conference, pages 140 and 141, February 1989. An example of a SECTOR ERASE is found in the paper entitled,"A 55 ns 0.35 .mu.m 5V Only 16 M Flash Memory with Deep-Power-Down", 1996, IEEE International Solid-State Circuits Conference, pages 44 and 45, February 1996.
Constraining the ERASE operation to either a SECTOR or BULK ERASE is done in consideration of the fact that when individual row lines are selected to be erased, there is the possibility the value stored on the floating gate of flash memory cells for unselected rows will be affected due to the occurrence of unintended tunneling. Accordingly, it is an object of the present invention to provide an erase mode wherein only a single row in a sector or multiple rows in a sector may be erased while reducing the disturb phenomenon for flash memory cells in the sector that are not selected.